Friday, August 19, 2011
MathCAD Tutorial
Please click the link below to view the MATHCAD Tutorial
http://www.engr.colostate.edu/ECE562/mathcad.pdf
Friday, June 17, 2011
Saturday, May 28, 2011
Tuesday, May 24, 2011
Antivirus Action Virus
Three heavy knocks on my bed room door, and my dad yelled: “Something is wrong with the computer because I could not access the website this morning. Could you fix it for me?” It was six o’clock on a Friday morning and I was still in bed. Lazily, I asked him what was wrong with the computer. My dad said that he did not know, but he could not access the Internet. I asked, “why not, what did you do?” I asked him what he did. I waited for any explanation from my dad, but outside my bedroom it was quiet. From experience, I predicted that my dad would sit in front of the computer and wait for me. I got out of bed and went downstairs to enter the family’s office.
As I entered the room, I heard my dad’s angry voice: “Did anyone else use the computer last night?” I realized that my prediction was correct. My dad sat on big black chair in front of the computer, and his face was red from anger. I asked: “Ok, dad, what is wrong with your computer and why can’t you access the Internet?” With his voice raised, he replied: “There was an error and the website was not displayed.” I pulled up a small chair (next to him) and asked: “Did you reboot the computer this morning?” He replied: “No, why do I have to reboot it?” The computer was turned off and on again. After the computer was turned on properly, my dad clicked the Internet icon. Then an error message popped up and the Internet was disabled. A Windows Security Alert message also appeared on the computer screen, informing us that the file “notepad.exe” was infected. It also asked us if we wanted to activate our antivirus software now. Then the Antivirus Action Rogue program automatically turned itself on and scanned the computer. I then decided to debug the system. Following are some pictures of antivirus action to help you to understand the problem better.
After a few hours of debugging and online research, I understood that the error message that appeared earlier was fake. This error message was in fact aimed at scamming the user into buying the “antivirus program”–which was actually a virus. This antivirus application configures itself to start when Windows logs in, and then runs a system scan, trying to make the user believe that his computer has been compromised by lots of infected files. My dad panicked and almost fell prey to this scam. I explained to my dad how the scam worked. We later found out that this antivirus was installed through the use of Trojans that hide themselves under the name of fake system scanners or video codecs (codes required for watching a video). This “Antivirus Action Virus” spreads itself by fake antivirus websites and contracted files uploaded on to file-sharing networks. Installation of Antivirus Action will allow it to change the system’s registry. The hacker is then able to control the infected PC as a remote host and able to steal your personal details. According to “Need to Remove Antivirus Action”, an article on Spyware-Expert.com “Antivirus Action is what is known as rogue spyware or ransomware, which means it claims to be legitimate security software but is actually spyware itself. It attempts to threaten you by bombarding you with fake security alerts and spyware scans; however, the larger threat that Antivirus Action poses is that hackers can use it to attempt to gain access to your sensitive information ( like passwords, account numbers, and credit cards). Because it can log keystrokes and Internet activity and then send that information to a remote server over the Internet – which can ultimately lead to identity theft.” Once I knew what the root cause of the error message was, I followed the instructions from an article above to remove the antivirus from my dad’s computer.
The above instructions are only applicable for Windows XP operating system but my dad’s computer operating system is Windows Vista; therefore, I was able to follow the instructions partly to remove the virus. I was able to execute the Mcafee security program to scan for any virus in the computer; however, the network was still not working correctly. Since the antivirus operated from the Internet and each time I tried to connect to the Internet new junk files were created. The only solution to this problem was to disconnect the computer from the Internet and reboot it after I removed all the new junk and registry entry files from the computer’s hard drive that were created by the antivirus software, I shut down the computer. I was crawled under the computer table to re-connect the computer to the Internet. I turned on the computer, clicked on the Internet icon and it worked. Below are some steps I used to remove the antivirus from my dad’s computer, so that they may help you—the reader— if your computer is infected (taken from www.antivirus.com)
1. Stop Antivirus Action process by pressing Ctrl+Alt+Del. Windows Task Manager will open. Look for the following process:
(random characters).exe
(random characters).exe
2. Shutdown the computer, unplug the entire internet wirers.
3. Find and delete all files that are created by antivirus action. These files are located inside software, program, antivirus, Microsoft run, and user directories.
4. Run a full system scan and clean/delete all detected infected file(s). A manual removal of virus-related files should also be performed.
5. Remove Antivirus Action start-up entry by going to Start > Run, type msconfig on the “Open” dialog box. System Configuration Utility will open. Go to Startup tab and uncheck the following Startup item(s): (random characters).exe agnz.exe
6. Delete Antivirus Action registry entries:
HKEY_CURRENT_USER\Software\Antivirus Action
HKEY_LOCAL_MACHINE\Software\Microsoft\Windows\CurrentVersion\Run “Antivirus Action”
HKEY_LOCAL_MACHINE\SOFTWARE\Microsoft\Windows\CurrentVersion\Uninstall\Antivirus Action
HKEY_LOCAL_MACHINE\Software\Microsoft\Windows\CurrentVersion\Run “Antivirus Action”
HKEY_LOCAL_MACHINE\SOFTWARE\Microsoft\Windows\CurrentVersion\Uninstall\Antivirus Action
7. Plug the entire internet wires, turn on the computer.
8. Just after the initial PC startup screen and just before the “Starting Windows” screen appears, press the F8 key.
9. Use the ↑ and ↓ keys on your keyboard to navigate to the “Safe Mode with Networking” choice. Press the “Enter” key to begin the safe mode boot up process.
10. Once your computer has booted into “Safe Mode with Networking“‘ Open Internet Explorer. Click on “Tools” and then choose “Internet Options”
11. Clear the box next to “Use a proxy server for your LAN”. Make sure the box next to “Automatically Detect Settings” is checked.
12. Open Internet Explorer and type www.spyware-experts.com/aa in the address bar to begin the download and installation of Spyware Doctor
13. Install Spyware Doctor with the default options and when the install is finished, Spyware Doctor will automatically begin to scan your computer. When the scan is complete, click the “Fix Checked” button and follow the instructions to complete the removal process. I use register Spyware Doctor to complete the removal process.
If you have the Windows Vista operating system and the Antivirus Action virus on your computer, then you can apply the above steps to debug and remove the virus from your computer. The above instructions will be very useful and could save you a couple of hours trying to find a solution yourself.
ATPG tools from Mentor Graphic Company
A few days ago, an old friend of mine from college called and asked me, “Have you ever used Mentor Graphic and ORCAD tools before? Can you tell me how they work?” I replied, “Yes, I have.” When I worked at Intel and Colorado State University, I applied these tools to generate scan test vectors, design, and layout a circuit.
Mentor Graphic is the name of a company which has supported many tools such as PCB design, TestKompress, BIST, Scan ATPG, EDT, DFT, and so on. These tools are very useful and beneficial for most Electrical, VLSI design, Test, and Design for Test engineers. These tools can help them verify and ensure that the output show that the circuit is working correctly. It can also help to pinpoint where the failure or problem is in the circuit. With current technology demands, the geometric size of a chip is getting smaller, its speed is faster, its frequency is higher, and its power requirements are lower. These tools have become handier and are essential for design and test engineers. These tools can save a lot of time when one is debugging or trying to resolve failure issues in the circuit.
In order to run and use these tools, one must have a license, support and access to the correct technology library from the Mentor Graphic company. Licenses for these tools are very expensive. It costs from fifteen to twenty five thousand dollars for one license. However, licenses can be shared among design engineers. As a result, large corporations such as Intel, only purchase a few licenses as they are needed. It is important for one to know and understand some basic error messages of the tools when you run them. Each error message has its own meaning; if one does not understand them, then it will take many hours to debug the problem and one is likely to miss the deadline. One must also understand how each command works, otherwise wrong test results will be output at the end. This will cost a huge amount of time to really debug the problem and waste a lot of money as well resources.
Each tool works differently and has its own advantages. As a result, different engineering tasks or projects would require using different tools to complete them. Most of the time, design engineers use three to four tools to complete their tasks. When I worked at Intel, I used the following tools from Mentor Graphic: TestKompress, EDT (Embedded Deterministic Test), and Low power EDT tools to debug and generate test vectors for stuck-at faults and at-speed tests in the 45nm and 32nm devices/chips (low power device and multiple clocks). The stuck-at test is used to minimize failure rate and ensure that the integrated circuit has no major physical issues or defects such as open, short and bridging. Individual signals and pins are assumed to be stuck at Logical '1', '0' and 'X'. For example, an output is tied to a logical 1 state during test generation to assure that a manufacturing defect with that type of behavior can be found with a specific test pattern. Likewise the output could be tied to a logical 0 to model the behavior of a defective circuit that cannot switch its output pin. However, not all faults can be analyzed using the stuck-at fault model. As a result, compensation for static hazards, namely branching signals, can render a circuit untestable using this model. An At-speed test is used to check the timing of the logic of a circuit change from one state to the next. Sometimes it is referred to as a transition fault. Today, in the nanometer design, at-speed testing is becoming more important and crucial in testing integrated circuits, as the geometric size is decreasing and clock speed is increasing. The At-speed test application allows a circuit to be tested under its normal operating conditions. However, fault simulation and test generation for standard transition faults become significantly more complex due to the requirement for handling faulty signal transitions that span multiple clock cycles. As a result, each transition fault needs to be considered multiple times, with multiple sizes of the extra delay on the faulty line. Fault detection potentially occurs when an unspecified value reaches a primary output. There are two methods for generating At-speed test patterns, Launch on Capture (LOC) and Launch off Shift (LOS). Each method has its own advantages and disadvantages. Some designs or circuits require one technique over the other. In the LOS method, the transition is launched during the last shift cycle from the scan path (non-functional). The scan enable is high during the last shift and must go low to enable response capture during the capture cycle. The time period for the scan enable signal to make this transition corresponds to the functional frequency. This method is not applicable for a very low cost ATE, which has a limitation of one at-speed port. The advantages for using the LOS method are high fault coverage, few test patterns and combination ATPG. The main disadvantage of the LOS method is requiring a fast scan enable signal. In the LOC method, the at-speed constraint on the scan enable signal port is relaxed and the transition is launched from the functional path. The controllability of launching a transition at the target gate is less as it depends on the functional response of the circuit under test to its initialization vector. The advantage of the LOC method is that there is no requirement for a fast scan enable signal. The disadvantages of LOC are medium fault coverage, more test patterns and sequential ATPG.
The flow for the ATPG tool is as follows the tool will read in a set of files including the netlist at gate level, the technology library, test protocol files such as constraint signal and clocks (dofile), and the test procedure or test setup. Next, it builds the model and performs design rule checking (DRC), the model process will be completed only if no violation error shows up. If there is an error message then debugging is required. The failure can occur in the netlist, library or test protocol files. The tool will create a fault list file only after the DRC step is completed. Test patterns will be generated after this step. The next step is fault coverage review. This step is required to understand the circuit and determine why the fault coverage is not meeting the specification. Sometimes, the company wants to publish or share the fault coverage with customers; therefore, one must have a solid understanding of the situation and answer why the fault coverage result is less than 100%. Otherwise, the management team will not be happy. Validation of the integrated circuit will be performed after the fault coverage result is satisfied. If there is no failure in the test during the validation step then the test patterns are saved and sent to manufacturing to test on the wafer.
When I worked at Colorado State University, I used ORCAD layout plus tools to design PCB (printed circuit board). This tool was developed by Cadence. It is a circuit board layout tool that accepts a layout-compatible circuit netlist from Capture CIS and generates an output layout file that is suitable for PCB fabrication. One must have the license, library and complete netlist of designs to run this Layout plus tool. If the netlist is not available, then use the ORCAD Capture CIS to create it. PCB layout is involved in importing netlists, placing components, routing and generating output files and reports. One must understand some basic steps and error messages of this tool. In general, layout plus command will give the output layout a file name which is the same as the input netlist file. If one changes the output file, do not change the file extension .max especially when one has to do the ECO (engineering change order) or debugging. In ECO mode, the layout plus command provides an ability to forward and back annotate the design flow. The forward annotate mode allows you to forward the change of your netlist from capture CIS schematic to the PCB. The back annotate mode allows you to export the change of your design in PCB back to schematic. You can set different options for the Auto ECO; the tool will update particular properties of the design according to the setting. The technology template contains information regarding layout design such as board layers, spacing, track widths, design rules, and so on. Sometimes, creating your own template is helpful in making a number of designs with the same set of rules and especially the design features are not provided in the template. If the footprint linking is in error or missing footprints on some components, then one will need to give the footprints to all missing components to complete the Auto ECO. Therefore, it is better to specify footprints to all parts during the schematic creation. One also must know how to debug any errors after layer stack, routing spacing, track-to-track, track-to-via, track-to-pad, via-to-via, via-to-pad and pad-to-pad spacing according to the recommendation of PCB manufacturer There are many other parameters that one must set and should be carefully checked with the recommended from PCB manufacturer. These parameters are drill sizes, pad stacks, minimum track width, and more. For a SMT (Surface Mount Technology) board, one needs to create fanout to rout a surface mount pad to via which provide a way to rout from the pad layer to any other layers. After the PCB design is completed without any error from DRC, the output or industry standard file for PCB fabrication is then generated. This file is also referred to as a Gerber file. It tells the machines in the PCB production process on how to draw patterns, makes traces, drills holes, and cut board. This process is called post process.
Now, you should have a clear understanding of what Mentor graphic and ORCAD tools are and how they work. The next time, if someone asks you about these tools, you can share with him/her how it they work. If you are a design engineer or planning to study this field, then this paper will give you a basic idea how these tools apply and why they are important and useful to know. If you are a DFT (design for test) engineer then the ATPG tools are required in your field. I knew and experienced this first hand because I had worked as a component design engineer and performed the DFT tasks at Intel for couple years.
Minh Anh Nguyen Resume
Minh Anh Thi Nguyen
6504 Lunar Court
Fort Collins, CO 80525
Home: (970)
223-7603
Objective
To obtain a
full-time position in Biomedical Engineering; I am really interested in
areas where I can apply my engineering experiences and skills, and my
knowledge of medical science , biomedical products, software quality assurance, and
software testing to develop and test medical devices that will help patients lead a comfortable life. My dedication in the job
will be helpful in achieving the company's goals and objectives.
Work Experiences
·
Software Testing/Quality Assurance Engineer-through
Aerotek (10/2011 - present)
KeySight
Technologies Loveland, CO
o
Duties included analyzing software requirements, writing
test plans, test scenario and test cases or requirements based on Functional
specifications, documenting and executing test cases to
the functionality of the application against the requirements manually. Generate bug reports and test
reports, retest and verify the bug fixes using Microsoft
Virtual Studio and Issue Viewer tools. Documented
test defects and procedures to enable accurate replication and ensure
compliance with standards. Provide developer teams with detailed reports on
quality metrics, identified bugs/flaws and recommended fixes.
o
Analyze test outputs to ensure actual test results meet
design and product requirements. Deliver thorough QA testing reports that
determined product quality and release readiness and good quality software program on time and meet production
level requirements.
o
Provide verification and validation testing across multiple
platforms included new hardware and software level for Military Special
projects.
This includes: SBIRS project, Themis project, CodeOne
project, Agilent PNA-X, PXA, Chassis, Millitech, Agilent 53230A, Universal
Frequency Counter/Time and
temperature control equipment using Virtual Rack, C++, ATEasy, Matlab, NI TestStand,
and LabView tools. Prepare
QA Status Summary Reports for each assignment. Installation
of Build, Patches and conduct testing on major release versions, Patches.
o
Perform black box, manual,
system install testing
prior to beta, UI, Basic Sanity, Functional, Data Validation and
Regression, User-acceptance testing of the application, and acceptance test documentation.
o
Work in multiple new feature teams to
accomplish product development goals and provide support for Quality.
o
Design defect
equipment tracking system and reporting to improve communications using
Microsoft Access tool.
·
Design Component Engineer (10/2005
– 12/2009)
Intel Corporation/Design Center Austin,
Texas
o
Wrote verilog models to validate ATPG
library and debug gates levels for Montecito (90nm) and
Tukwila (70nm), Intel
Siverthorne and Intel Lincroft (45nm), and Intel Penwell (32-nm)
devices. Created, translated, and simulated Scan vector test programs for these
devices using ATPG/Tmax tools, and Perl program and Structural Based Silicon
Debug test system. Analyzed and resolved low test coverage issues. Developed and implemented flows to generate Embedded
Deterministic Test module, ATPG Stuck-at and AT-speed scan tests for these devices
using scan compression and ATPG tools.
o
Wrote
Perl script to automate setup, find new release netlists in central datebase
and execute DRC procedure to verify the overall connection of scan chain at
gate-level before result publishing; generated the DRC test report, and sent alert
design failed message and test report to design and test teams. This script is
a great help in reducing test time and tracking design mistakes or failure
problems.
o
Developed and executed an effective diagnostic
flow to identify scan test pattern failures using YieldAssist Testkompress
tool. This flow is helpful to run diagnostic tools for identifying ATPG
test failures quickly, and to enhance and reduce debug time significantly.
·
Test Vector Generation Engineering
(04/2004
- 10/2005)
Agilent
Technologies, Inc. Fort
Collins, CO
o
Used VHDL and Test Benches to verify that the
overall design and algorithms worked correctly. Developed, translated,
simulated and debugged RAM, PLL, and Stuck-at Fault vector test programs
for TSMC90nm and TSMC130nm devices using Automatic Test Pattern
generators (ATPG)/Tmax tools and Design For Testability. Developed a technical
method to define and isolate any hardly found failures in electronic package
using TDR tools.
o
Ensured
that Agilent 93000, 83000 and temperature controller equipment are functioning properly and
safely. Developed and documented a new procedure to evaluate and bring up
Agilent's first world-wide 12-inch TEL Prober (wafer test equipment), and
released it to production. Developed a test script to automate, analyze,
extract, calculate and plot characterization data from test result files using
Perl. This test script is designed to improve test time and reduce costs.
o
Created an eRoom (team project communication)
website to communicate, provide and update information to the Test team.
·
Power Electronics, Lab Teaching Assistant (08/2003 - 04/2004)
Colorado State University Fort Collins, CO
o
Oversaw graduate level courses in Power
Electronic Design. Helped students with Power electronic labs and Pspice,
MATLAB, and MATHCAD simulations. Responsible for the course website, providing
and grading homework and lab solutions.
Academic Medical devices projects at Colorado State University (CSU)
·
Gold nanoparticle RF research Associate (Voluntary) (08/2015 - present)
Chemistry and Electrical Engineering departments -CSU Fort Collins, CO
o
Research and study of the release of heat by
targeted gold nanoparticles exposed to RF fields. Design, and simulate coils
which will be used in some experiments on the heating of enzymes.
o
Build the coils by using exactly all
materials and values which are specified during my calculation and simulation
runs. Test these coils and collect all test data to prove that
the experiments work.
o
Clearly
document all test procedures and test results to maximize understanding by
potential audiences from varying backgrounds.
o Research and study
the physical properties of gold nanoparticles influence their RF thermal
delivery, which will aid in the further development of nanoscale materials for
the treatment of cancer and various biomedical applications.
·
Centrifuge Loading Human Factors on
Medical device project (8/2015- 5/2016)
Terumo BCT-Colorado State University Fort Collins, CO
o Successfully developed a working prototype
procedure that will assist users with centrifuge
leak issues for loading of a complex disposable tube
set onto a centrifuge of the Spectra Optia device. This procedure helped in eliminating
centrifuge leaks caused by human errors, which is very important because these
leaks cause a loss of blood components and terminate the patient's procedure
before it is completed. It decreases the effect on the patient and improves the quality of the
medical device.
o
Responsible for create
a grant chart to plan and schedule project using Excel, test plan, test scripts,
and test procedures without using the requirement and/or design documents;
Matlab and Labview codes to analyze and compare both image and audio
files. Negotiate price, purchase,
set-up, testing a microphone and software
to record audio files. Prepare tables and graphs of data analyses and present this
data to the research team in team meetings. Perform the
following software testing methods: unit, shake out, black box, white box, and
regression. Ensure that the project complies with the following
requirements: Quality System Regualtion FDA 21 CFR 820.30, FDA 21
CFR 820.40, and FDA 21 CFR 820.180”, which are required for design and document
controls, and records. Ensure that the project
complies the Medical Device Regulation ISO
9000 Quality Standardsand the ISO 9001 protocol for Design and Manufacturing.
o Installed a microphone and a camera inside the machine
to record the signal and take an image
after each loading procedure and then compare this signal and image with a
correct loading signal and image; if one audio or image file is not correctly
set, then an error message will display to alert users to correct the problem
before they continue.
· Clinical
practicum/internship gold
nanoparticle RF research (1/2014 – 5/2014)
School of Biomedical Engineering Colorado
State University
o
Successfully designed and simulated coils, which
is used in some experiments on the heating of enzymes. Mathcad and Ansoft HFSS
(High Frequency Structural Simulator), used to design and simulate these
coils. Mathcad software is used for
verification, validation, documentation and calculations on characteristics of
these coils. Ansoft HFSS is a 3D
Electromagnetic Field solver, which is used for antenna design, and the design
of complex RF electronic circuit elements including filters, transmission
lines, transformers, capacitors, etc.
Two kinds of coils will be modeled: transformers and parallel capacitor
plates. The radio frequency of these
coils is 13.3 MHz, and copper materials are used to build these coils.
·
Biomedical Signal and Image Processing
(01/2014 - 05/2016)
School of
Biomedical Engineering Colorado State University
o
Wrote Matlab script to analyze and find ECG QRST
wave detection.
o
Wrote Matlab script to calculate and determine ECG
heart rate.
o
Wrote Matlab script to identify body organs and
cancer cells of CT and MRI image.
Professional
Computer & Engineering Skills
·
Computer programming Skills: Perl, C++,
UNIX, Linux, Cygwin, MATLAB, and DOS
·
Operating System: Windows XP/Vista7, 8
·
Medical Devices: ECG
and Ultrasound machines, and Oximeters
·
Grasped concepts on imaging modalities like MRI, fMRI, CT,
SPECT, PET, ECG, EEG.
·
Experience in statistics and digital signal acquisition and
analysis, automatic control, electronics and circuit theory, computer
interfacing techniques.
·
In-depth knowledge of the use principles of science,
mathematics and bio-engineering to design, implement, and evaluate hardware and
software solutions to bio-engineering problems.
·
Experience with software development lifecycle processes
Education
Colorado State
University Fort Collins, CO
Bachelor of
Science in Biomedical Engineering Graduated in May 2016
Bachelor of
Science in Electrical (hardware) Engineering Graduated in May 2016
Colorado State University
Fort Collins, CO
Bachelor of
Science in Electrical (software) Engineering Graduated in May 2001
(BSECE: Concentration in Computer
Engineering), Minor
in Computer Science,
Certifications / Awards:
o School of
Biomedical Engineering Achievement and Pioneering certification, 2016
o Mentorship
program, Colorado Bioscience Institute’s, 2015 -2016
o Certified Nurse
Aide, State of Colorado, 2013 - 2017
o Centrifuge
Loading Human Factors on Medical device
project first place award, 2016
o
A patent application file entitled “PB0944-US01 Detection of
Loading Errors”, 2016
References
Will
be pleased to provide upon request.
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