ATPG tools from Mentor Graphic Company

A few days ago, an old friend of mine from college called and asked me, “Have you ever used Mentor Graphic and ORCAD tools before? Can you tell me how they work?” I replied, “Yes, I have.” When I worked at Intel and Colorado State University, I applied these tools to generate scan test vectors, design, and layout a circuit.

Mentor Graphic is the name of a company which has supported many tools such as PCB design, TestKompress, BIST, Scan ATPG, EDT, DFT, and so on. These tools are very useful and beneficial for most Electrical, VLSI design, Test, and Design for Test engineers.  These tools can help them verify and ensure that the output show that the circuit is working correctly. It can also help to pinpoint where the failure or problem is in the circuit. With current technology demands, the geometric size of a chip is getting smaller, its speed is faster, its frequency is higher, and its power requirements are lower.   These tools have become handier and are essential for design and test engineers. These tools can save a lot of time when one is debugging or trying to resolve failure issues in the circuit.

In order to run and use these tools, one must have a license, support and access to the correct technology library from the Mentor Graphic company.  Licenses for these tools are very expensive. It costs from fifteen to twenty five thousand dollars for one license.  However, licenses can be shared among design engineers. As a result, large corporations such as Intel, only purchase a few licenses as they are needed.  It is important for one to know and understand some basic error messages of the tools when you run them. Each error message has its own meaning; if one does not understand them, then it will take many hours to debug the problem and one is likely to miss the deadline. One must also understand how each command works, otherwise wrong test results will be output at the end. This will cost a huge amount of time to really debug the problem and waste a lot of money as well resources.  

Each tool works differently and has its own advantages. As a result, different engineering tasks or projects would require using different tools to complete them. Most of the time, design engineers use three to four tools to complete their tasks.  When I worked at Intel, I used the following tools from Mentor Graphic: TestKompress, EDT (Embedded Deterministic Test), and Low power EDT tools to debug and generate test vectors for stuck-at faults and at-speed tests in the 45nm and 32nm devices/chips (low power device and multiple clocks). The stuck-at test is used to minimize failure rate and ensure that the integrated circuit has no major physical issues or defects such as open, short and bridging. Individual signals and pins are assumed to be stuck at Logical '1', '0' and 'X'. For example, an output is tied to a logical 1 state during test generation to assure that a manufacturing defect with that type of behavior can be found with a specific test pattern. Likewise the output could be tied to a logical 0 to model the behavior of a defective circuit that cannot switch its output pin. However, not all faults can be analyzed using the stuck-at fault model. As a result, compensation for static hazards, namely branching signals, can render a circuit untestable using this model. 
An At-speed test is used to check the timing of the logic of a circuit change from one state to the next. Sometimes it is referred to as a transition fault. Today, in the nanometer design, at-speed testing is becoming more important and crucial in testing integrated circuits, as the geometric size is decreasing and clock speed is increasing. The At-speed test application allows a circuit to be tested under its normal operating conditions. However, fault simulation and test generation for standard transition faults become significantly more complex due to the requirement for handling faulty signal transitions that span multiple clock cycles. As a result, each transition fault needs to be considered multiple times, with multiple sizes of the extra delay on the faulty line. Fault detection potentially occurs when an unspecified value reaches a primary output. There are two methods for generating At-speed test patterns, Launch on Capture (LOC) and Launch off Shift (LOS). Each method has its own advantages and disadvantages. Some designs or circuits require one technique over the other. In the LOS method, the transition is launched during the last shift cycle from the scan path (non-functional). The scan enable is high during the last shift and must go low to enable response capture during the capture cycle.  The time period for the scan enable signal to make this transition corresponds to the functional frequency.  This method is not applicable for a very low cost ATE, which has a limitation of one at-speed port. The advantages for using the LOS method are high fault coverage, few test patterns and combination ATPG. The main disadvantage of the LOS method is requiring a fast scan enable signal. In the LOC method, the at-speed constraint on the scan enable signal port is relaxed and the transition is launched from the functional path.  The controllability of launching a transition at the target gate is less as it depends on the functional response of the circuit under test to its initialization vector.  The advantage of the LOC method is that there is no requirement for a fast scan enable signal. The disadvantages of LOC are medium fault coverage, more test patterns and sequential ATPG.

The flow for the ATPG tool is as follows the tool will read in a set of files including  the netlist at gate level, the technology library, test protocol files such as constraint signal and clocks (dofile), and the test procedure or test setup. Next, it builds the model and performs design rule checking (DRC), the model process will be completed only if no violation error shows up.  If there is an error message then debugging is required. The failure can occur in the netlist, library or test protocol files. The tool will create a fault list file only after the DRC step is completed. Test patterns will be generated after this step. The next step is fault coverage review. This step is required to understand the circuit and determine why the fault coverage is not meeting the specification.  Sometimes, the company wants to publish or share the fault coverage with customers; therefore, one must have a solid understanding of the situation and answer why the fault coverage result is less than 100%. Otherwise, the management team will not be happy.  Validation of the integrated circuit will be performed after the fault coverage result is satisfied. If there is no failure in the test during the validation step then the test patterns are saved and sent to manufacturing to test on the wafer.

When I worked at Colorado State University, I used ORCAD layout plus tools to design PCB (printed circuit board).  This tool was developed by Cadence.  It is a circuit board layout tool that accepts a layout-compatible circuit netlist from Capture CIS and generates an output layout file that is suitable for PCB fabrication.  One must have the license, library and complete netlist of designs to run this Layout plus tool. If the netlist is not available, then use the ORCAD Capture CIS to create it.  PCB layout is involved in importing netlists, placing components, routing and generating output files and reports.  One must understand some basic steps and error messages of this tool. In general, layout plus command will give the output layout a file name which is the same as the input netlist file. If one changes the output file, do not change the file extension .max especially when one has to do the ECO (engineering change order) or debugging.  In ECO mode, the layout plus command provides an ability to forward and back annotate the design flow. The forward annotate mode allows you to forward the change of your netlist from capture CIS schematic to the PCB. The back annotate mode allows you to export the change of your design in PCB back to schematic.  You can set different options for the Auto ECO; the tool will update particular properties of the design according to the setting. The technology template contains information regarding layout design such as board layers, spacing, track widths, design rules, and so on.  Sometimes, creating your own template is helpful in making a number of designs with the same set of rules and especially the design features are not provided in the template.  If the footprint linking is in error or missing footprints on some components, then one will need to give the footprints to all missing components to complete the Auto ECO. Therefore, it is better to specify footprints to all parts during the schematic creation.  One also must know how to debug any errors after layer stack, routing spacing, track-to-track, track-to-via, track-to-pad, via-to-via, via-to-pad and pad-to-pad spacing according to the recommendation of PCB manufacturer  There are many other parameters that one must set and should be carefully checked with the recommended from PCB manufacturer. These parameters are drill sizes, pad stacks, minimum track width, and more.  For a SMT (Surface Mount Technology) board, one needs to create fanout to rout a surface mount pad to via which provide a way to rout from the pad layer to any other layers. After the PCB design is completed without any error from DRC, the output or industry standard file for PCB fabrication is then generated. This file is also referred to as a Gerber file. It tells the machines in the PCB production process on how to draw patterns, makes traces, drills holes, and cut board.  This process is called post process.

Now, you should have a clear understanding of what Mentor graphic and ORCAD tools are and how they work. The next time, if someone asks you about these tools, you can share with him/her how it they work.  If you are a design engineer or planning to study this field, then this paper will give you a basic idea how these tools apply and why they are important and useful to know.  If you are a DFT (design for test) engineer then the ATPG tools are required in your field.  I knew and experienced this first hand because I had worked as a component design engineer and performed the DFT tasks at Intel for couple years.